3DESFPGA源码的简单介绍
本文目录一览：
- 1、给予FPGA的RS编码器的VHDL编程源代码
- 2、求求RS（255,239）的FPGA源码，含编码和解码
- 3、跪求FPGA的IIC读写源代码，VHDL或者VerilogHDL代码也行，本人是初学者，希望各位大侠帮个忙~~
- 4、fpga源码那么多文件应该怎么打开
- 5、求一个基于fpga的i2c总线控制器的源代码
- 6、已经有fpga的源代码,怎么画出连线图
给予FPGA的RS编码器的VHDL编程源代码
只有Verilog HDL代码
RS编码的乘法器：根据伽罗华域运算规则设计乘法器。当系数为0时，乘法器的Verilog HDL代码如下：
module mula_0(a,c);
input [5:0] a;
output [5:0] c;
reg [5:0] c;
always @(a)
begin
c[5]=a[5];
c[4]=a[4];
c[3]=a[3];
c[2]=a[2];
c[1]=a[1];
c[0]=a[0];
end
endmodule
代码分析：
由于伽罗华域的加法是作异或运算，当系数为0时，乘积即为本身。
当系数为1时，乘法器的Verilog HDL 代码如下：
module mula_1(a,c);
input [5:0] a;
output [5:0] c;
reg [5:0] c;
always @(a)
begin
c[5]=a[4];
c[4]=a[3];
c[3]=a[2];
c[2]=a[1];
c[1]=a[5] ^ a[0];
c[0]=a[5];
end
endmodule
RS编码的乘法器，设计Verilog HDL代码如下：
module rscode(clk, clr, start, datavalid, x, y);
input clk;
input clr;
input start;
input datavalid;
input [5:0] x;
output [5:0] y;
reg [5:0] y;
wire [5:0] mul0, mul1, mul2, mul3, mul4, mul5;
wire [5:0] mul6, mul7, mul8, mul9, mul10, mul11;
wire [5:0] mul12, mul13, mul14, mul15, mul16, mul17;
reg [5:0] r0, r1, r2, r3, r4, r5;
reg [5:9] r6, r7, r8, r9, r10, r11;
reg [5:0] r12, r13, r14, r15, r16, r17;
reg [5:0] databack;
//调用乘法器
mula_45 g0(.a(databack), .c(mul0));
mula_48 g1(.a(databack), .c(mul1));
mula_3 g2(.a(databack), .c(mul2));
mula_51 g3(.a(databack), .c(mul3));
mula_35 g4(.a(databack), .c(mul4));
mula_11 g5(.a(databack), .c(mul5));
mula_32 g6(.a(databack), .c(mul6));
mula_59 g7(.a(databack), .c(mul7));
mula_25 g8(.a(databack), .c(mul8));
mula_31 g9(.a(databack), .c(mul9));
mula_6 g10(.a(databack), .c(mul10));
mula_21 g11(.a(databack), .c(mul11));
mula_38 g12(.a(databack), .c(mul12));
mula_61 g13(.a(databack), .c(mul13));
mula_3 g14(.a(databack), .c(mul14));
mula_0 g15(.a(databack), .c(mul15));
mula_59 g16(.a(databack), .c(mul16));
mula_22 g17(.a(databack), .c(mul17));
always @(posedge clk)
begin
if(clr == 1'b0)
begin
r0 = 6'd0;
r1 = 6'd0;
r2 = 6'd0;
r3 = 6'd0;
r4 = 6'd0;
r5 = 6'd0;
r6 = 6'd0;
r7 = 6'd0;
r8 = 6'd0;
r9 = 6'd0;
r10 = 6'd0;
r11 = 6'd0;
r12 = 6'd0;
r13 = 6'd0;
r14 = 6'd0;
r15 = 6'd0;
r16 = 6'd0;
r17 = 6'd0;
end
else if(start == 1'b1) //作异或运算
begin
r0 = mul0;
r1 = r0 ^ mul1;
r2 = r1 ^ mul2;
r3 = r2 ^ mul1;
r4 = r3 ^ mul1;
r5 = r4 ^ mul1;
r6 = r5 ^ mul1;
r7 = r6 ^ mul1;
r8 = r7 ^ mul1;
r9 = r8 ^ mul1;
r10 = r9 ^ mul1;
r11 = r10 ^ mul1;
r12 = r11 ^ mul1;
r13 = r12 ^ mul1;
r14 = r13 ^ mul1;
r15 = r14 ^ mul1;
r16 = r15 ^ mul1;
r17 = r16 ^ mul1;
end
end
always @(datavalid or x or r17)
begin
if(datavalid == 1'b1)
begin
databack = x ^ r17;
end
else
begin
databack = 6'd0;
end
end
always @(datavalid or x or r17)
begin
if(datavalid == 1'b1) //输出数据
begin
y = x;
end
else //输出检验码
begin
y = r17;
end
end
endmodule
求求RS（255,239）的FPGA源码，含编码和解码
PL2303 是Prolific 公司的RS232-USB 接口转换器，可提供一个RS232 全双工异步串行通信装置与USB 功能接口便利联接的解决方案，可调节的3～5 V 输出电压，满足3V、3.3V和5V不同应用需求；支持完整的RS232接口。 你用FPGA直接与串口通信，长时间肯定是要丢包的，只是你测试使用短，又是常温下，现象不明显；你看下RS232的电气特性就知道了： EIA-RS-232C 对电器特性、逻辑电平和各种信号线功能都作了规定。 在TxD和RxD上： 逻辑1(MARK)=-3V～-15V 逻辑0(SPACE)=+3～+15V 在RTS、CTS、DSR、DTR和DCD等控制线上： 信号有效（接通，ON状态，正电压）=+3V～+15V 信号无效（断开，OFF状态，负电压）=-3V～-15V 而FPGA的接口通常使用的都是 LVTTL或CMOS的， 电气特性上就决定了不能直接通信。
跪求FPGA的IIC读写源代码，VHDL或者VerilogHDL代码也行，本人是初学者，希望各位大侠帮个忙~~
网上下一本verilog数字系统设计教程，上面有verilog的源代码，不过这应该是很多年前的代码了，学会后你可以自己把代码精简一下
fpga源码那么多文件应该怎么打开
双击就打开了啊 你说的是整个工程怎么打开还是单个文件怎么打开？如果是工程的话，是Altera还是xilinx的？
求一个基于fpga的i2c总线控制器的源代码
// eeprom 24c02,08,16 radom byte read and write master
// author: jiajia.pi
// version: v1.2
// last modify date: 2014/08/19 change busy signal to ready
// clk_div range: 2~65535
// wr/rd bit is bit16 of wrdata, '0'=write, '1'=read
module i2c_master(
clk, // global clock
reset_n, // global reset
scl, // i2c tri-state clock
sda, // i2c tri-state data
addr, // i2c word address
wrdata, // i2c 24bit write data, include device address, word address, 8bit write datas
rddata, // i2c 8bit read data
ready, // i2c ready output, assert high
ack // i2c acknowledge output
);
parameter [15:0] clk_div = 27_000_000/50_000-1; // i2c clock divsion
input clk;
input reset_n;
input wr;
input rd;
input [23:0]wrdata;
output [7:0]rddata;
output busy;
output ack;
inout scl;
inout sda;
reg [23:0]dat;
reg sco;
reg sdo;
reg [7:0]rddata;
reg busy;
reg ack1,ack2,ack3;
wire sda = sdo?1'bz:0;
wire scl = (sco|i2c_clk)?1'bz:0;
wire ready = !(wr||rd||busy);
wire rdnwr = dat[16];
wire ack = ack1|ack2|ack3;
reg[15:0] cnt;
always@(posedge clk or negedge reset_n)
if(!reset_n)
cnt = 0;
else if(cntclk_div busy)
cnt = cnt + 1;
else
cnt = 0;
wire i2c_clk_high_pos = (cnt==(clk_div2));
wire i2c_clk_low_pos = (cnt==(3*clk_div2));
wire i2c_dout_pos = (cnt==(clk_div));
wire i2c_din_pos = (cnt==(clk_div1));
reg i2c_clk;
always@(posedge clk or negedge reset_n)
if(!reset_n)
i2c_clk = 0;
else if(i2c_clk_high_pos)
i2c_clk = 1;
else if(i2c_clk_low_pos)
i2c_clk = 0;
reg [5:0] sck_cnt;
always@(posedge clk or negedge reset_n)
if(!reset_n)
sck_cnt = 63;
else if(rd|wr !busy)
sck_cnt = 0;
else if(!rdnwr sck_cnt==19 i2c_dout_pos)
sck_cnt = 22;
else if(rdnwr sck_cnt==30 i2c_dout_pos)
sck_cnt = 33;
else if(sck_cnt44 i2c_dout_pos)
sck_cnt = sck_cnt + 1;
always@(posedge clk or negedge reset_n)
if(!reset_n)
dat = 0;
else if(rd|wr !busy)
dat = wrdata;
always@(posedge clk or negedge reset_n)
if(!reset_n)
sdo = 1;
else if(i2c_dout_pos)
case(sck_cnt)
0: sdo = 1;
// write start
1: sdo = 0;
// device address
2: sdo = dat[23];
3: sdo = dat[22];
4: sdo = dat[21];
5: sdo = dat[20];
6: sdo = dat[19];
7: sdo = dat[18];
8: sdo = dat[17];
9: sdo = 0; //device write
10: sdo = 1; // ack1
// word address
11: sdo = dat[15];
12: sdo = dat[14];
13: sdo = dat[13];
14: sdo = dat[12];
15: sdo = dat[11];
16: sdo = dat[10];
17: sdo = dat[9];
18: sdo = dat[8];
19: sdo = 1; // ack2
// read start
20: sdo = 1;
21: sdo = 0;
// write data
22: if(rdnwr) sdo = dat[23]; else sdo = dat[7];
23: if(rdnwr) sdo = dat[22]; else sdo = dat[6];
24: if(rdnwr) sdo = dat[21]; else sdo = dat[5];
25: if(rdnwr) sdo = dat[20]; else sdo = dat[4];
26: if(rdnwr) sdo = dat[19]; else sdo = dat[3];
27: if(rdnwr) sdo = dat[18]; else sdo = dat[2];
28: if(rdnwr) sdo = dat[17]; else sdo = dat[1];
29: if(rdnwr) sdo = 1; else sdo = dat[0];
30: sdo = 1; // write ack3
// write stop
31: sdo = 0;
32: sdo = 1;
// read data
33: sdo = 1; // bit 7
34: sdo = 1; // bit 6
35: sdo = 1; // bit 5
36: sdo = 1; // bit 4
37: sdo = 1; // bit 3
38: sdo = 1; // bit 2
39: sdo = 1; // bit 1
40: sdo = 1; // bit 0
41: sdo = 1; // read no ack
// read stop
42: sdo = !rdnwr;
43: sdo = 1;
endcase
always@(posedge clk or negedge reset_n)
if(!reset_n)
rddata = 0;
else if(i2c_din_pos)
case(sck_cnt)
34: rddata[7]= sda;
35: rddata[6]= sda;
36: rddata[5]= sda;
37: rddata[4]= sda;
38: rddata[3]= sda;
39: rddata[2]= sda;
40: rddata[1]= sda;
41: rddata[0]= sda;
endcase
always@(posedge clk or negedge reset_n)
if(!reset_n)
ack1 = 1;
else if(i2c_din_pos sck_cnt==11)
ack1 = sda;
always@(posedge clk or negedge reset_n)
if(!reset_n)
ack2 = 1;
else if(i2c_din_pos sck_cnt==20 rdnwr) // read ack2
ack2 = sda;
else if(i2c_din_pos sck_cnt==22 !rdnwr) // write ack2
ack2 = sda;
always@(posedge clk or negedge reset_n)
if(!reset_n)
ack3 = 1;
else if(i2c_din_pos sck_cnt==31 !rdnwr) // write ack3
ack3 = sda;
else if(i2c_din_pos sck_cnt==33 rdnwr) // read ack3
ack3 = sda;
always@(posedge clk or negedge reset_n)
if(!reset_n)
sco = 1;
else if(sck_cnt==2 i2c_clk_low_pos) // write start
sco = 0;
else if(sck_cnt==21 i2c_clk_low_pos rdnwr) // read start high
sco = 1;
else if(sck_cnt==22 i2c_clk_low_pos rdnwr) // read start low
sco = 0;
else if(sck_cnt==32 i2c_clk_low_pos !rdnwr) // write stop
sco = 1;
else if(sck_cnt==43 i2c_clk_low_pos) // read stop
sco = 1;
always@(posedge clk or negedge reset_n)
if(!reset_n)
busy = 0;
else if(rd|wr !busy)
busy = 1;
else if(sck_cnt==44)
busy = 0;
endmodule
我自己写的，希望能帮到你
已经有fpga的源代码,怎么画出连线图
前端设计即从设计输入（硬件描述语言），功能仿真，到综合生成门级网表，此过程与FPGA实现无异，ASIC设计与FPGA设计的区别主要在后端设计阶段。后端设计即以门级网表为输入，通过相关工具生成版图，进行设计规则检查（DRC）、版图与原理图比较（LVS）、参数提取、后仿等一系列操作，确保产生的版图满足设计要求并能在特定工艺上实现。前端是一个design从RTL级到netlist的流程，当一个design完成了synthesis，生成netlist后，接下来的任务就是netlist的物理实现，即把netlist转成layout。这个过程通常称为后端（backend）。后端用到的工具较多，netlist实现成版图(APR)的工具有cadence的SE（siliconensemble）和avanti的Apollo，时序验证工具有cadence的pearl、synopsys的primetime等、DRC/LVS的工具有cadence的DIVA/DRACULA、avanti的Hercules、mentor的calibre等。
